Logic state analyzers are used to monitor and record sequences of states that occur in a collection of digital signals in a system under test. A "state" is simply any one of the 2.sup.n logical patterns that n-many digital signals may experience. A sequence of addresses or a sequence of fetched instructions are examples of electrical activity describable as states in a microprocessing environment and that can be monitored by a logic state analyzer to record their "state flow."
To monitor the ongoing sequence of states in a system under test a logic state analyzer samples the electrical values of the signals of interest at times determined by one or more clock signals associated with the system under test. The sampled electrical values obtained are compared to thresholds of selected value and polarity to determine their logical values, each of which will be either true or false, one or zero. Each resulting collection of ones and zeros for a sample is a state in the ongoing sequence of states. It is also simply a binary value that may be stored in a memory. A series of such stored values is a record of the activity occurring in the system under test. Such a record may be termed a trace.
To store an indefinitely long record or trace of such activity would require a corresponding indefinitely large memory. This is impractical for at least two reasons. First, the cost of huge memories is prohibitive. Second, and more to the point, no human being using a logic state analyzer has time to sort through several hundred thousand stored states, or even a few tens of thousands, to find the data that is meaningful for the problem under investigation. Yet this could easily be required if it were necessary to trace an entire high level transaction such as finding the tangent of an angle, or reading a file from a mass storage peripheral. What are needed are ways to reduce the amount of trace data stored to manageable proportions while ensuring that the information in the trace is most likely to be pertinent to the investigation at hand.
Accordingly, logic state analyzers are typically equipped with sufficient memory to store traces that range from a few hundred to a few thousand states. The memories are used circularly. That is, the newest data to be stored is written in the memory location currently containing the oldest data. The size of the memory is then the size of the trace, which then always reflects the last "memory's worth" of activity occurring to that time.
The storage of state data into the memory halts subsequent to the detection of some specified condition in the incoming state data. That condition is called the trigger condition, or simply the trigger. If the storage of state data halts immediately upon the detection of the trigger the trace then represents the activity that preceded the trigger. This can be called an "end-on" trigger. If the storage of state data were instead to continue for one additional "memory's worth" of state data the trace would then represent the activity that occurred after the trigger. This can be called a "start-on" trigger. Typically, the user specifies some number of additional storage operations that is less than one memory's worth, e.g., half that number of locations. This produces a "center-on" trigger. A "center-on" or any other "middle of trace" trigger produces a trace that records both what states led up to the trigger, as well as those that followed it.
One of the ways to help ensure that the trace contains principally the data that is most likely to be pertinent to the investigation at hand is to allow the trigger to represent a condition more sophisticated than simply any occurrence of a specified state. A sequential trigger, for instance, produces a trigger only when a predefined sequence of states has already occurred previous to the trigger state. In terms of a flow chart for the state flow of the system under test, the user can use a sequential trigger to say "trigger when it gets there by going that way." That is, simply getting "there" is not sufficient to create a trigger; getting "there" must also be preceded, in order, by certain other events (states) that represent "going that way." For example, the trigger may be desired upon fetching an instruction from the first address in a complement routine, but only if that routine is called in the context of floating point division, not for floating point subtraction, etc. Thus, sequential triggering allows the user to specify a trigger condition that is not simply a mere place on a flow chart, but is one that has historical criteria associated with it as well.
Sequential triggering is accomplished by equipping a logic state analyzer with a mechanism to allow the user to define a sequence of states to precede a designated trigger state and a sequence detection mechanism to issue an appropriate internal trigger signal upon detection of the trigger state subsequent to the satisfaction of the sequence.
It may also be convenient to equip a logic state analyzer having a sequential trigger with a restart capability. This useful feature allows the detection of a specified state to cancel the progress made to that time toward satisfaction of the sequence, requiring satisfaction to begin afresh.